This invention relates to a processor in which pipelined parallel processing is performed by an operand effective address arithmetic unit for calculating the operand effective address necessary to execute an instruction and an instruction execution unit for performing the operation of the instruction, and more particularly to a processor which is suitable to perform an operation with a larger bit width than a basic arrangement at a high speed.
In a case where an operation is to be performed for data with a data length being longer than a basic part, e.g. the operation of 64 bit data is to be performed by a basic arithmetic unit for 32 bit data, previously known processors time-divisionally operate high order 32 bit data and low order 32 bit data, or, as disclosed in JP-A-59-201145, adds another arithmetic unit for expansion to the basic arithmetic unit so as to constitute a new arithmetic unit for 64 bit data.
However, the former example takes a very long time in performing the operation of the data length exceeding that of the basic arithmetic unit, and the latter example requires increased hardware although it can process 64 bit data at a time.
A processor in which the calculation of the effective address of an operand and the execution of an instruction are performed in a pipelined fashion, in order to implement the pipelined processing, causes individual controllers to individually operate the address arithmetic unit and the instruction execution unit. As mentioned above such a pipeline system processor, if the arithmetic unit for instruction execution is for 32 bits, operates 64 bit data in such a manner that the 64 bit data is divided into high order 32 bits and low order 32 bits which are individually operated by the 32 bit arithmetic unit. In this case, in order to obviate the increase of operation time, the prior art pipeline processor is provided with another 32 bit arithmetic unit to permit the data length of 64 bits to be processed by the entire arithmetic unit. However, this leads to the undesired increase of hardware (twice in the hardware of the arithmetic unit).